Input/output circuits have utilized delay chains to delay an incoming signal by a known amount. Delay is achieved by transmitting a signal through a concatenated chain of finite delay elements, or stages. However, the delay per stage is not known precisely. In other words, the predicted delay per stage does not correspond to the actual delay per stage. This uncertainty is particularly large in new technologies, making it difficult to design the correct chain length. If too short of a chain is utilized, a chain leads to non-working interface circuit.
Accordingly, the inventors herein have recognized a need for a system for determining a delay time interval of each component utilized in a delay chain of components.